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projects:hifi:retrofitting_coaxial_spdif_out [2022/09/23 01:48] – admin | projects:hifi:retrofitting_coaxial_spdif_out [2024/10/24 12:41] (current) – admin | ||
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====== Retrofitting coaxial spdif out ====== | ====== Retrofitting coaxial spdif out ====== | ||
- | This page describes how to add to a device | + | This page describes how to add to a device |
The modification described on this page is to add a coaxial spdif output to a Sony MDS-JE520 MiniDisc deck. Although it contains both an optical and coaxial spdif input, it only contains an optical spdif output. The lack of a coaxial spdif output is inconvenient and this modification mitigates that. | The modification described on this page is to add a coaxial spdif output to a Sony MDS-JE520 MiniDisc deck. Although it contains both an optical and coaxial spdif input, it only contains an optical spdif output. The lack of a coaxial spdif output is inconvenient and this modification mitigates that. | ||
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==== Some theory: Impedance matching for a resistor voltage divider network ==== | ==== Some theory: Impedance matching for a resistor voltage divider network ==== | ||
- | S/PDIF signals are defined in IEC 60958-3 (2003)((Digital audio interface, Part 3)). The output shall have a substantial resistive impedance | + | The complete schematic drawing |
- | Based on the definition above, we have two considerations to take into account: (1) Adapt the output voltage to match the 0.5 v and (2) make sure the output impedance matches $75\ \Omega$. | + | | {{ :projects: |
+ | | //Schematic of spdif coax interface// | ||
- | [schematic] | + | The schematic |
+ | |||
+ | S/PDIF signals are defined in IEC 60958-3 (2003)((Digital audio interface, Part 3)). The output shall have a substantial resistive impedance of $(75\ \pm\ 15) (\Omega)$ when measured at frequencies from 0.1 MHz to 128 times the maximum frame rate, which equals to about 5.6 MHz for a sample rate of 44.1 kHz. The signal amplitude shall be $(0.5\ \pm\ 0.1 ) {\text V}$ peak-to-peak, | ||
+ | |||
+ | Based on the definition above, we have two considerations to take into account: (1) Adapt the output voltage to match 0.5 v and (2) make sure the output impedance matches $75\ \Omega$. But since the output level is specified at a $75\ \Omega$ load, the actual voltage divider need to double the output, since half of the voltage is dissipated in the load resistor. | ||
Given the following resistor voltage divider: | Given the following resistor voltage divider: | ||
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Please note that under load, when the impedance is connected to Vout, the voltage measured at Vout will reduce to exactly half the voltage in comparison to when it is open. | Please note that under load, when the impedance is connected to Vout, the voltage measured at Vout will reduce to exactly half the voltage in comparison to when it is open. | ||
+ | ==== Measurements ==== | ||
+ | |||
+ | | {{ : | ||
+ | | // | ||